1. Field of the Invention
This invention relates to integrated circuits in general and, more particularly, to a system-on-a-chip using dynamically reconfigurable logic islands interconnected by fall-through FIFOs for flexible pipeline processing.
2. Description of Related Art
Computer systems have traditionally comprised a system unit or housing which comprises a plurality of electrical components comprising the computer system. A computer system typically includes a motherboard which is configured to hold the microprocessor and memory and the one or more busses used in the computer system. The motherboard typically comprises a plurality of computer chips or electrical components including intelligent peripheral devices, bus controllers, processors, bus bridges, etc.
More recently, computer systems are evolving toward an integration of functions into a handful of computer chips. This coincides with the ability of chip makers to place an increasingly large number of transistors on a single chip. For example, currently chip manufacturers are able to place in excess of 50 million transistors on a single integrated circuit or monolithic substrate. It is anticipated that within several years chip makers will be able to place more than 500 million transistors on a single chip. Thus, computer systems are evolving toward comprising a handful of computer chips, where each computer chip comprises a plurality of functions. Moreover, manufacturing a unique variant of a system-on-a-chip for each different application are is very expensive because of the high cost of mask sets (i.e. tooling) for the sub-micron fabrication required for dense systems-on-a-chip. What is needed is a system and method that will bring manufacturing economies of scale to a broad varieties of applications through dynamically reconfigurable logic networks for flexible pipeline processing in a system-on-a-chip.
Additionally, strings of separate logic integrated circuits connected in a daisy-chain fashion suffer from clocking problems. Each logic device must use the clocking of the device feeding it. Therefore, an improved system-on-a-chip architecture is desired which overcomes these problems, allowing each collection of logic to operate semi-autonomously from its neighbors while buffering speed and load variations between pipeline stages.